A conventional digital to analog converter (DAC) employs circuit cells that use a simple switched current mirror approach. This simple and effective approach is efficient at generating high-precision static output current values representing the analog output at low frequencies of digital input signal changes. However, the same circuit may behave differently when stepped dynamically at high rates or frequencies (e.g., gigahertz (GHz) frequencies) of digital input signal changes. At higher rates or frequencies, the analog output of the conventional DAC circuit cell is often distorted.
For example, a triangular analog output (voltage or current) waveform pattern may be generated from a simple conventional DAC by a repeating stair step up and down pattern of digital input signals. At low speeds switching frequencies (almost DC) of the digital input signal, the output from the conventional DAC has an ideal stair-case type output current profile, with each step being equal. However, oftentimes when the conventional DAC is stepped at faster rates, a memory effect occurs. With the memory effect, the next output DAC step size depends on the pattern of the previous steps of output. Instead of the DAC having a linear output with respect to the digital input, the analog output of the conventional DAC becomes non-linear, varying with the switching speeds of the digital input signal. Even if the digital input signal is monotonically switched at the same frequency, the higher frequency switching speeds show how the memory effect can distort the analog signal output.
There are a few conventional ways to overcome the memory effect in a DAC. One conventional way is to add substantial capacitance to the output of a bias circuit to minimize voltage spikes from charge injection on a bias voltage coupled to the DAC circuit cells. A disadvantage to adding capacitance is that it consumes significant surface area of an integrated circuit increasing die size and increasing per die costs of a semiconductor wafer. Increased die size lowers potential profits of an integrated circuit.
Another conventional method is to use current steering circuit cells that steer currents between the analog output and a dummy load instead of the circuit cell that switches currents on and off into the analog output. The current steering circuit cell in the DAC minimizes charges that may be injected back into the biasing circuit and the bias voltage. However, current steering circuit cells are disadvantageous because they constantly consume power and are thus not power efficient. Accordingly, current steering circuit cells that steer current are costly due to power consumption and are not useful in low-power DAC applications.
Thus, conventional methods of improving frequency response of a DAC are costly due to increased die size or increased power consumption. It is desirable to improve the DAC current switching cell design over that of the prior art for use at higher frequencies of digital input signal changes.